1. Field of the Invention
The present invention relates to the field of digital to analog converters.
2. Background Art
The rapid expansion in the performance of digital computing and digital signal processing has made it possible to store, manipulate, process and even generate large amounts of data. It has enabled rapid information retrieval and sorting of large informational databases and the subsequent communication of the information around the world. It has enabled analysis of very large complex systems ranging from electronic circuitry, to physical structures, to weather and the movement and detection of astronomical bodies.
The expansion in computational capability has been so great that this time period is frequently referred to as the digital age. This has tended to mask the fact that much of the world, including the actual sensing of physical data, the actual changing of physical conditions, and the actual information communication processes remains analog. In digitally controlled machines, the motors, position sensors, video detectors and optical positioning devices, laser measurement or cutting subsystems, are among the many analog circuits that are controlled by the digital output from a computer or DSP. Even in the central processing units of the digital computers themselves, device switching between digital states and transfer of information can frequently appear to be more like analog than digital operations as clock speeds approach the state of the art at the time. Most important of all, human senses are analog. This creates a major need for analog-to-digital (A/D) and digital-to-analog converter (DAC) circuitry that is fast, handles large amounts of digital data and does not significantly distort or loose information in the analog signal.
Referring to FIG. 1, a representative DAC application is symbolically indicated. Digital Signal Source 100 provides source signal information in digital format to DAC 110. Complexity can vary from a simple addressable buss interface and holding register to a complete DSP with memory, clock generators, controllers, and any other system components. DAC 110 converts said source signal into an analog output signal that is passed to Analog Load 120. Analog Load 120 may be the final stage of a system such as a display or it may be a transmission stage to subsequent stages. Within Analog Load 120 or subsequent circuit stages, the DAC analog output signal may be converted to a digital format using an A/D converter.
A digital signal synthesizer system refers to combination of a Digital Signal Source 100 and one or more DAC 110 circuits wherein Digital Signal Source 100 includes means to configure digital input signals and control signals to DAC 110. Typically, a digital signal synthesizer system will include more than one DAC and may have more than one operating frequency band in which it generates signals. In a more restricted form, digital signal synthesizer systems may generate a limited set of predetermined wave shapes such as sinusoidal, square wave, pulse, or triangular waves.
FIG. 2 illustrates the minimum signal interface between Digital Signal Source 100 and DAC 110. In addition to signal data bits and a clock, DAC 110 may have multiple other control inputs. These may come from Digital Signal Source 100, other circuits, or from control signals originating external to the system partially illustrated in FIG. 1. Examples of additional input controls frequently provided in a DAC are shown in FIG. 4.
The largest number of bits commonly used is 24. The large number of bits provides sufficient resolution for the analog signal so that the distortion is very low. Values below 70 dB are common. The minimum number of bits used is 1. One use of a 1-bit DAC is in microwave and millimeter wave applications such as radar systems.
Use of a large number of bits severely limits the clock rate. A 24-bit DAC is limited to a clock rate of about 100 KHz with present technology. As the maximum allowed clock rate is increased, the cost of the DAC can raise to many times the cost of one that is not close to existent, technology limitations. The combination of high resolution, low distortion and low clock speed makes the use of 24-bit DAC circuits common in audio entertainment system applications.
High clock rates find frequent uses in systems requiring large amounts of data to be updated frequently. Video displays for gaming, simulators, and military systems are examples. Sample rates of several hundred million per second for a 16-bit DAC are possible but 14-bit and even 12-bit are used in addition to lowering the sample rate in order to alleviate the high cost of such devices.
FIG. 3 illustrates a typical 12-bit, high speed DAC of the present art and is provided to illustrate the general type and amount of circuitry present in this type of device. An 8-bit device would be similar but have 4 fewer sections in the portion not shown. A DAC may have either a voltage or current output. Complementary voltage outputs are the most common although a single output may be provided for applications internal to an integrated circuit providing additional functionality. A current output DAC will typically have differential outputs with output current miss-match held below a specified upper limit. The output currents will not be identical and the output circuitry normally includes either impedances from each to ground or other means to accommodate the imbalance.
FIG. 4 illustrates an example 400 of a typical application of a high resolution, high speed, current output DAC. DAC U401 is coupled to Digital Signal Source 100 at nodes N401 through N415 and N417. Nodes N401 through N414 couple the digital data inputs. The digital clock is coupled at node N415. A power down control signal is coupled at node N417. A power down signal is a typical input control among several possible control signals that are common to DAC circuits in general.
One of the common features for this type of application is the use of one or two resistors to set the full-scale output signal level, which is a current level in example 400. Current setting resistor R401 is coupled to DAC U401 at node N418. DAC U401 possesses another common feature, an internal reference with an option of utilizing an external one. The internal reference is selected by coupling the selection pin to ground at node N420. Capacitors C401 and C404 function as bypass noise filter capacitors. Capacitor C401 couples the external reference input pin to ground at node N419, and capacitor C404 couples the bypass connection to ground at node N427.
Another common feature of DACs is the use of separate power and ground returns for the digital and analog portions of the DAC. In example 400, DAC U401 is coupled to analog power A401 at node N422, to digital power D401 at node N423, to analog ground AGND401 at node N421 and to digital ground DGND401 at node N424. The use of separate digital and analog power and ground circuits helps to reduce distortion of the analog output due to coupling of digital switching noise onto it through the power and ground connections internal to the DAC integrated circuit. Power supply filtering and bypass capacitors are not shown. External to DAC U401, the digital ground and analog ground may be connected to a common ground plane or maintained separately. Analog and digital power connections typically will have separate filtering and bypass capacitors even if the DAC operates from a single supply voltage.
Operating bandwidth of DAC U401 is limited by external capacitor C402 operating in conjunction with circuitry internal to DAC U401. Capacitor C402 couples the Bandwidth Limit control input at node N416 to analog power input A401 at node N422.
Capacitor C405 and resistor R403 couple the non-inverting output at node N425 to ground at node N421. Capacitor C403 and resistor R402 couple the inverting output at node N426 to ground at node N421. Capacitors C403 and C405 are small and function to filter any clock signal and any of its harmonic signals from the output waveform. Clock feed-through can be a major system problem and require much more sophisticated filtering and control methods to remove it without distorting the analog output signal. Resistors R402 and R403 accommodate a minimum current flow and are the least sophisticated method of limiting the impact of any current imbalance between the complimentary outputs. Since the output impedance of the DAC is typically a couple of hundred thousand ohms, R402 and R403 values should be selected to avoid significant movement of the output, offset voltage from ground. For particular applications, said values can range up to several megohms but are typically much smaller.
Transformer T401 couples the output of DAC U401 to the analog load block 120. The transformer primary couples the non-inverting output of DAC U401 at node N425 to the inverting output at node N426. The secondary of transformer T401 couples the input to the analog load at node N428 to the analog input return at node N429. Use of coupling transformer T401 insures that the currents driving the load are the same from each output of DAC U401. Care should also be taken so that the transformer itself does not introduce significant distortion in the output waveform.
FIGS. 5 through 14 are illustrations of DAC outputs of the present art and the generic forms and relative amounts of distortion present as a function of the number of bits of resolution and the number of sample time points per cycle. Said figures further provide a basis for comparison to the reduced distortion outputs of embodiments of the present invention with comparable resolution and sample rate.
FIG. 5 illustrates a simple, single frequency sine wave plus a dc component. Although most waveforms are complex combinations of multiple sine waves and the presence of multiple frequencies and phases can exacerbate distortion, a single cycle is used for visual clarity. The presence of a dc offset also complicates the illustrations and understanding. For example, in FIG. 5, all of the rectangular sample bars are exclusively positive whereas in FIG. 6, they are both positive and negative as would generally be expected in a sine wave. Since removal and restoration of a dc offset is almost always a simple process, a single frequency sine wave without a dc component, as shown in FIG. 6, is used in subsequent illustrations. The number of sample time points per cycle in FIGS. 5 and 6 is 34. Although many applications use a much higher rate, a rate of 34 per cycle would be within the normal sampling range for both high-resolution audio and high frequency video applications. A sample rate of 34 per cycle is used except where the rate is being varied to illustrate the impact of such variation.
FIGS. 7 through 12 illustrate the effects of the number of bits of resolution used to form the analog signal. FIG. 7 illustrates a representation of the reference sine wave for a 1-bit DAC. FIG. 8 illustrates the envelope of the clocked output signal. The output signal is severely distorted with various forms of distortion apparent in the illustration. Most prominent is the deviation during the period wherein the value of the sine wave has yet to exceed the threshold for the next bit. It should be noted that the reference sine wave and the output signal do not coincide until after the sine wave has peaked. There is also a small time delay or phase shift distortion.
FIG. 9 illustrates a representation of the reference sine wave for a 2-bit DAC, and FIG. 10 illustrates the envelope of the output signal. Comparing FIG. 9 to FIG. 7 and FIG. 10 to FIG. 8, the distortion is reduced. The maximum transition step size is smaller, and the deviation that occurs before the reference sine wave crosses the threshold value for the next bit transition is reduced. The time delay and phase shift are also smaller although they typically will not pose problems as significant as amplitude distortion.
FIG. 11 illustrates a representation of the reference sine wave for a 5-bit DAC, and FIG. 12 illustrates the envelope of the output signal. Comparing FIG. 11 to FIG. 9 and FIG. 12 to FIG. 10, the distortion is further reduced with the increased number of bits. The maximum transition step size is again smaller, and the deviation that occurs before the reference sine wave crosses the threshold value for the next bit transition is reduced. The time delay and phase shift are also smaller. A further increase in the number of bits continues to reduce signal distortion but except for an enlargement of a small area of a waveform, visual illustration becomes impractical. Such an enlargement can be seen in FIG. 19B, and although the magnitude of the distortion is greatly reduced, its form remains largely unchanged until the magnitude of a bit is less than the noise floor of the system.
FIG. 13 illustrates the distortion that may be introduced in the output waveform by the sample rate of the digital input signal. FIG. 14 illustrates the envelope of the output waveform. Note the asynchronous relationship between the output signal and the sample clock. This is the more general case. The digital input from which the waveform is generated has 7 samples per cycle, just under over one fifth of that in FIG. 6. This is more than 3 times the Nyquist criterion so that all of the information necessary to reproduce the sine wave is theoretically available. Signal distortion is of the same form as that associated with the number of bits of resolution. Both the time delay and phase distortion are more sensitive to a relatively low number of samples per cycle than to a relatively low number of bits per sample.
The obvious result is that low distortion representation of a signal is best achieved with a very large number of bits per sample and a very large number of samples per cycle at the maximum frequency component of interest in the signal. In addition, the DAC should be designed for low harmonic and inter-modulation distortion resulting from the non-linear characteristics of individual circuit components. These results may be somewhat obvious and DAC manufacturers have applied new designs and processes to increase DAC capabilities in both respects. The major difficulty is cost that can increase exponentially as the state of the art in speed is approached.